programmable high-frequen cy crystal oscillato r with spread spectrum (ssxo) cy25701 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07684 rev. *a revised august 31, 2004 features ? crystal oscillator with spread spectrum clock (ssc) ? wide operating output (ssclk) frequency range ? 10?166 mhz ? programmable spread spectrum with nominal 31.5 khz modulation frequency ? center spread: 0 .25% to 2.0% ? down spread: ?0.5% to ?4.0% ? integrated phase-locked loop (pll) ? low cycle-to-cycle jitter ? 3.3v operation ? output enable function benefits ? provides wide range of spread percentages for maximum electromagnetic interference (emi) reduction, to meet regulatory agency electromagnetic compliance (emc) requirements. reduces devel- opment and manufacturing costs and time-to-market . ? eliminates the need for external crystal oscillator . ? internal pll to generate up to 166 mhz output . ? suitable for most pc, consumer, and networking applications . ? application compatibility in standard and low-power systems . logic block diagram pll with modulation control programmable configuration output dividers and mux 1 4 2 vdd vss oe rfb c xout c xin 3 ssclk pin configuration cy25701 4-pin plastic smd 4 oe 3 vdd 1 2 vss ssclk
cy25701 document #: 38-07684 rev. *a page 2 of 7 functional description the cy25701 is a spread spectr um crystal oscillator (ssxo) ic used for the purpose of reducing emi found in today?s high-speed digital electronic systems. the device uses a cypress proprietary pll and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the embedded input crystal. by frequency modulating the clock, the measured emi at the fundamental and harmonic frequencies are gr eatly reduced. this reduction in radiated energy can sign ificantly reduce the cost of complying with regulatory agency (emc) requirements and improve time-to-market without degrading system perfor- mance. the cy25701 uses a factory-programmable configuration memory array to synthesize output frequency and spread%. the spread% is programmed to either center spread or down spread with various spread percentages. the range for center spread is from 0.25% to 2.00%. the range for down spread is from ?0.5% to ?4.0%. contact the factory for smaller or larger spread% amounts if required. refer to table 2 for spread selection values. the frequency modulated ssclk output can be programmed from 10?166 mhz. the cy25701 is available in a 4-pin plastic smd package with operating temperature range of ?20 to 70 c. programming description factory-programmable cy25701 factory programming is available for samples and manufac- turing by cypress. all requests must be submitted to the local cypress field application engineer (fae) or sales represen- tative. once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. this part number will be used for additional sample requests and production orders. additional information on the cy25701 can be obtained from the cypress web site at www.cypress.com. output frequency, ssclk output (ssclk, pin 3) the modulated frequency at the ssclk output is produced by synthesizing the embedded crystal oscillator frequency input. the range of synthesized clock is from 10?166 mhz. spread percentage (ssclk, pin 3) the ssclk spread can be programmed to various spread percentage values from 0.25% to 2.0% for center spread and from ?0.5% to ?4.0% for down spread. refer to table 2 for available spread options frequency modulation (ssclk, pin 3) the frequency modulation is programmed at 31.5 khz for all ssclk frequencies from 10 to 166 mhz. contact the factory if a higher-modulation frequency is required. pin definition pin name description 1oe output enable pin : active high . if oe = 1, ssclk is enabled. 2 vss power supply ground . 3 ssclk spread spectrum clock output . 4vdd 3.3v power supply . table 1. programming data requirement pin function output frequency spread percent code frequency modulation pin name ssclk ssclk ssclk pin# 3 3 3 units mhz % khz program value enter data enter data 31.5 table 2. spread percent selection center spread code a b c d e f percentage 0.25% 0.5% 0.75% 1.0% 1.5% 2.0% down spread code g h j k l m percentage ?0.5% ?1.0% ?1.5% ?2.0% ?3.0% ?4.0%
cy25701 document #: 38-07684 rev. *a page 3 of 7 absolute maximum rating supply voltage (vdd) .. .............. .............. ...... ?0.5v to +7.0v dc input voltage....................................?0.5v to v dd + 0.5v storage temperature (non-condensing) .... ?55c to +100c junction temperature ................................ ?40c to +125c data retention @ tj = 125 c................................> 10 years package power dissipation...................................... 350 mw operating conditions parameter description min. typ. max. unit v dd supply voltage 3.00 3.30 3.60 v t a ambient temperature ?20 ? 70 c c load max. load capacitance @ pin 3 ? ? 15 pf f ssclk ssclk output frequency, c load = 15 pf 10 ? 166 mhz f mod spread spectrum modulati on frequency 30.0 31.5 33.0 khz t pu power-up time for vdd to reach minimum specified voltage (power ramp must be monotonic) 0.05 ? 500 ms dc electrical characteristics parameter description condition min. typ. max. unit i oh output high current (pin 3) v oh = v dd ? 0.5, v dd = 3.3v (source) 10 12 ? ma i ol output low current (pin 3) v ol = 0.5, v dd = 3.3v (sink) 10 12 ? ma v ih input high voltage (pin 1) cmos levels, 70% of v dd 0.7v dd ?v dd v v il input low voltage (pin 1) cmos levels, 30% of v dd ? ? 0.3v dd v i ih input high current (pin 1) v in = v dd ??10 a i il input low current (pin 1) v in = v ss ??10 a i oz output leakage current (pin 3) th ree-state output, oe = 0 ?10 ? 10 a c in [1] input capacitance (pin 1) pin 1, or oe ? 5 7 pf i vdd supply current v dd = 3.3v, ssclk = 10 to 166 mhz, c load = 0, oe = v dd ??30ma ac electrical characteristics [1] parameter description condition min. typ. max. unit dc output duty cycle ssclk, measured at v dd /2 45 50 55 % t r output rise time 20%?80% of v dd, c l = 15pf ? ? 2.7 ns t f output fall time 20%?80% of v dd, c l = 15pf ? ? 2.7 ns t ccj1 [2] cycle-to-cycle jitter ssclk (pin 3) ssclk 133 mhz, measured at v dd /2 ? ? 200 ps 25 mhz ssclk <133 mhz, measured at v dd /2 ? ? 400 ps ssclk < 25 mhz, measured at v dd /2 ? ? 1% of 1/ssck s t oe1 output disable time (pin1 = oe) time from falling edge on oe to stopped outputs (asynchronous) ? 150 350 ns t oe2 output enable time (pin1 = oe) time from rising edge on oe to outputs at a valid frequency (asynchronous) ? 150 350 ns t lock pll lock time time for ssclk to reach valid frequency ? ? 10 ms ? f aging in frequency t a = 25c, first year ?5 ? 5 ppm notes: 1. guaranteed by characterization, not 100% tested. 2. jitter is configuration dependent. actual jitter is dependent on output frequencies, spread percentage, temperature, and outp ut load. for more information, refer to the application note, ?jitter in pll base d systems: causes, effects, and solutions? available at http://www.cypress.com/cloc k/appnotes.html, or contact your local cypress field application engineer.
cy25701 document #: 38-07684 rev. *a page 4 of 7 application circuit switching waveforms 0.1uf vdd 1 23 4 oe vss ssclk vdd power cy25701 duty cycle timing (dc = t 1a /t 1b ) t 1a t 1b ssclk output rise/fall time ssclk tr v dd 0v tf output rise time (tr) = (0.6 x v dd )/sr1 (or sr3) output fall time (tf) = (0.6 x v dd )/sr2 (or sr4) refer to ac electrical characteristics table for sr (slew rate) values. output enable/disable timing ssclk v dd t oe1 v il v ih output enable 0v (asynchronous ) high impedance t oe2
cy25701 document #: 38-07684 rev. *a page 5 of 7 informational graphs [3] spread spectrum profile: fnom=166mhz, fmod=30khz, spread%= -4% 172.5 171.5 170.5 169.5 168.5 167.5 166.5 165.5 164.5 163.5 162.5 161.5 160.5 159.5 fnominal 0 20 40 60 80 100 120 140 160 180 200 time (us) spread spectrum profile: fnom=166mhz, fmod=30khz, spread%= +/-1% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 162.5 spread spectrum profile: fnom=66mhz, fmod=30khz, spread%= -4% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 68.5 68 67.5 67 66.5 66 65.5 65 64.5 6 4 63.5 spread spectrum profile: fnom=66mhz, fmod=30khz, spread%= +/-1% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 67.5 67 66.5 66 65.5 65 64.5 ordering information part number [4] package description product flow cy25701jxczzzz 4-lead plastic je smd ? lead free commercial, ?20 to 70c CY25701JXCZZZZT 4-lead plastic je smd, tape and reel ? lead free commercial, ?20 to 70c notes: 3. the ?informational graphs? are meant to convey the typical perf ormance levels. no performance specifications is implied or gu aranteed. refer to the tables on pages 4 and 5 for device specifications. 4. ?zzzz? denotes the assigned product dash number. this number will be assigned by factory after the output frequency and sprea d percent programming data is received from the customer.
cy25701 document #: 38-07684 rev. *a page 6 of 7 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimension all product and company names mentio ned in this document are the tradema rks of their respective holders. dimensions in millimeters 5.0 (10.5 max) (5.8 max) 10.20.3 5.60.2 0.51 5.080.1 0.150.1 2.4 2.5 (0.05 min) (2.7 max) +0.2 -0.1 3.6 1.00.2 (1.0) 1.00.2 (1.0) 1 4 5.08 1.3 2.1 4.6 recommended soldering pattern 0.1 reference jedec: n/a pkg. weight: 0.24 gms 4-lead je04a 51-85204-**
cy25701 document #: 38-07684 rev. *a page 7 of 7 document history page document title: cy25701 pr ogrammable high-frequ ency crystal oscillator wi th spread spectrum (ssxo) document #: 38-07684 rev. *a rev. ecn no. issue date orig. of change description of change ** 224108 see ecn rgl new data sheet *a 258974 see ecn rgl corrected the product suffix ( lead free) in the ordering information table and added note 4.
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